# On the computation of the reciprocal of floating point expansions using an adapted Newton-Raphson iteration

* Corresponding author
1 LAAS-MAC - Équipe Méthodes et Algorithmes en Commande
LAAS - Laboratoire d'analyse et d'architecture des systèmes
2 ARIC - Arithmetic and Computing
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Many numerical problems require a higher computing precision than that offered by common floating point (FP) formats. One common way of extending the precision is to represent numbers in a \emph{multiple component} format. With so-called \emph{floating point expansions}, numbers are represented as the unevaluated sum of standard machine precision FP numbers. This format offers the simplicity of using directly available and highly optimized FP operations and is used by multiple-precisions libraries such as Bailey's QD or the analogue Graphics Processing Units tuned version, GQD. In this article we present a new algorithm for computing the reciprocal FP expansion ${a}^{-1}$ of a FP expansion $a$. Our algorithm is based on an adapted Newton-Raphson iteration where we use "truncated" operations (additions, multiplications) involving FP expansions. The thorough error analysis given shows that our algorithm allows for computations of very accurate quotients. Precisely, after $i\geq0$ iterations, the computed FP expansion $x=x_0+\ldots+x_{2^i-1}$ satisfies the relative error bound: $\abs{\frac{x-a^{-1}}{a^{-1}}}\leq 2^{-2^i(p-3)-1}$, where $p>2$ is the precision of the FP representation used ($p=24$ for single precision and $p=53$ for double precision).
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Cited literature [12 references]

https://hal.archives-ouvertes.fr/hal-00957379
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Submitted on : Monday, March 10, 2014 - 12:07:09 PM
Last modification on : Monday, July 4, 2022 - 10:17:03 AM
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• HAL Id : hal-00957379, version 1

### Citation

Mioara Joldes, Jean-Michel Muller, Valentina Popescu. On the computation of the reciprocal of floating point expansions using an adapted Newton-Raphson iteration. 25th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP, Jun 2014, Zurich, Switzerland. pp.8. ⟨hal-00957379⟩

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