A Digital Sine-Weighted Switched-Gm mixer for Single-Clock Power-Scalable Parallel Receivers

Abstract : This paper presents a mixed A/D architecture for parallel channelized RF receiver applications. Its power consumption scales with the number of active receivers and hence with the available overall data rate. A digital sine-weighted switched-Gm mixer with a DDFS per channel is proposed as a zero-IF mixer. The DDFS of all channels are programmable via a Look up Table and are driven by a single central clock. Each channel also exploits a 2-path filter to increase selectivity and interference robustness. To demonstrate the concept two parallel receivers were implemented in a 28nm UTBB FD-SOI CMOS, with 9.5mW/receiver, achieving 40dB of dynamic range, 13dB NF and better than 75 dB inter-receiver isolation.
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Communication dans un congrès
IEEE Custom Integrated Circuits Conference, Apr 2017, Austin, United States. IEEE Custom Integrated Circuits Conference, 4p., 2017, 〈http://ieee-cicc.org/〉
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Reda Kasri, Eric Klumperink, Philippe Cathelin, Éric Tournier, Bram Nauta. A Digital Sine-Weighted Switched-Gm mixer for Single-Clock Power-Scalable Parallel Receivers. IEEE Custom Integrated Circuits Conference, Apr 2017, Austin, United States. IEEE Custom Integrated Circuits Conference, 4p., 2017, 〈http://ieee-cicc.org/〉. 〈hal-01539447〉

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