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Communication Dans Un Congrès Année : 2016

High performance CMOS FDSOI devices activated at low temperature

Résumé

3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).
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Dates et versions

hal-01730659 , version 1 (13-03-2018)

Identifiants

Citer

L. Pasini, P. Batude, J. Lacord, M. Cassé, B. Mathieu, et al.. High performance CMOS FDSOI devices activated at low temperature. 2016 IEEE Symposium on VLSI Technology, Jun 2016, Honolulu, United States. ⟨10.1109/VLSIT.2016.7573407⟩. ⟨hal-01730659⟩
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