Abstract : Memory access duration on multicore architectures are highly variable, since concurrent accesses to resources by different cores induce time interferences. Consequently, critical software tasks may be delayed by non-critical ones, leading to deadline misses and possible catastrophic failures. We present an approach to tackle the implementation of mixed criticality work-loads on multicore chips, focusing on task chains, i.e., sequences of tasks with end-to-end deadlines. Our main contribution is a Monitoring & Control Agent able to stop non-critical software execution in order to prevent memory interference and guarantee that critical tasks deadlines are met. This paper describes our approach, and the associated experimental framework to conduct experiments to analyze attainable real-time guarantees on a multicore platform.
https://hal.laas.fr/hal-02465340
Contributor : Daniel Loche
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Submitted on : Monday, February 3, 2020 - 6:21:36 PM
Last modification on : Friday, February 7, 2020 - 4:40:11 PM
Daniel Loche, Michaël Lauer, Matthieu Roy, Jean-Charles Fabre. Safe Scheduling on Multicores: an approach leveraging multi-criticality and end-to-end deadlines. 10th European Congress on Embedded Real Time Software and Systems (ERTS 2020), Jan 2020, TOULOUSE, France. ⟨hal-02465340⟩
