Skip to Main content Skip to Navigation
Journal articles

Compact Modeling of 3D Vertical Junctionless Gate-allaround Silicon Nanowire Transistors Towards 3D Logic Design

Abstract : To sustain transistor scaling beyond lateral 7nm devices, gate-all-around (GAA) junctionless vertical nanowire field effect transistors (JLNT) are one of the promising alternatives. To overcome the roadblocks of logic cell design using this emerging technology, this work explores compact modeling of 3D GAA-JLNTs based on physics of junctionless transport. The model features an explicit continuous analytical form of drain current calculations adapted for a 14 nm channel junctionless nanowire transistor (JLNT) technology and has been validated against extensive characterization results on a wide range of JLNT geometry, depicting good accuracy. Finally, preliminary simulations have been explored for performance assessment of logic circuits, such as inverters with passive load, active load and complementary topologies as well as ring oscillators, designed using the developed JLNT compact model.
Complete list of metadata

https://hal.archives-ouvertes.fr/hal-03429568
Contributor : Chhandak Mukherjee Connect in order to contact the contributor
Submitted on : Monday, November 15, 2021 - 5:28:33 PM
Last modification on : Tuesday, November 23, 2021 - 3:44:26 AM

File

SSE_fullpaper_EUROSOI-ULIS_VF....
Files produced by the author(s)

Identifiers

Citation

Mukherjee Chhandak, Arnaud Poittevin, Ian O'Connor, Guilhem Larrieu, Cristell Maneux. Compact Modeling of 3D Vertical Junctionless Gate-allaround Silicon Nanowire Transistors Towards 3D Logic Design. Solid-State Electronics, Elsevier, 2021, 183, pp.108125. ⟨10.1016/j.sse.2021.108125⟩. ⟨hal-03429568⟩

Share

Metrics

Record views

29

Files downloads

29