Skip to Main content Skip to Navigation
Book section

3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model

Abstract : Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices, which are well suited to pursue scaling beyond lateral scaling limitations around 7 nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model, which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50 nm. We used this model to simulate the projected performance of inverter logic gates based on passive load, active load and complementary topologies and to carry out a performance exploration for the number of nanowires in transistors. In terms of compactness, through a dedicated full 3D layout design, we also demonstrate a 48% reduction in lateral dimensions for the complementary structure with respect to 7 nm FinFET-based inverters.
Document type :
Book section
Complete list of metadata

https://hal.laas.fr/hal-03371673
Contributor : Guilhem Larrieu Connect in order to contact the contributor
Submitted on : Friday, October 8, 2021 - 6:23:42 PM
Last modification on : Tuesday, October 19, 2021 - 11:18:10 PM

Links full text

Identifiers

Citation

Arnaud Poittevin, Chhandak Mukherjee, Ian O’connor, Cristell Maneux, Guilhem Larrieu, et al.. 3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model. VLSI-SoC: Design Trends, 621, Springer International Publishing, pp.301-321, 2021, IFIP Advances in Information and Communication Technology, ⟨10.1007/978-3-030-81641-4_14⟩. ⟨hal-03371673⟩

Share

Metrics

Record views

18