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Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor

Bruno Neckel Wisling 1 Marina Deng 1 Chhandak Mukherjee 1 Magali de Matos 1 Abhishek Kumar 2 Guilhem Larrieu 2 Jens Trommer 3 Thomas Mikolajick 3 Cristell Maneux 1
1 IMS - Laboratoire de l'intégration, du matériau au système
2 LAAS-MPN - Équipe Matériaux et Procédés pour la Nanoélectronique
LAAS - Laboratoire d'analyse et d'architecture des systèmes
3 NaMLab gGmbH
Abstract : In this paper, we present an improved methodology to extract the small-signal electrical equivalent circuit of the parasitic elements using RF test structures for a 3D vertical nanowire transistor technology. The methodology is based on the extraction of the distributed parasitic elements from an open structure for which on-wafer S-parameter measurements were carried out up to 40 GHz. The electrical equivalent circuit of the passive device was then used for de-embedding of the transistor S-parameters for extraction of intrinsic smallsignal parameters such as the gate capacitances.
Keywords : Test structure Equivalent circuit Parasitic components RF measurements De-embedding
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Journal articles
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https://hal.archives-ouvertes.fr/hal-03657781
Contributor : Chhandak Mukherjee Connect in order to contact the contributor
Submitted on : Tuesday, May 3, 2022 - 12:18:25 PM
Last modification on : Wednesday, May 4, 2022 - 3:48:32 AM

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LAAS-MICRO-NANO-BIO-TECHNOLOGIES | LAAS-MPN | LAAS | UNIV-TLSE3 | IMS-BORDEAUX-FUSION | UT1-CAPITOLE | UNIV-TLSE2 | INSA-TOULOUSE | IMS-BORDEAUX | INSA-GROUPE | ANR | CNRS

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Bruno Neckel Wisling, Marina Deng, Chhandak Mukherjee, Magali de Matos, Abhishek Kumar, et al.. Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor. Solid-State Electronics, Elsevier, 2022, 194, pp.108359. ⟨10.1016/j.sse.2022.108359⟩. ⟨hal-03657781⟩

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