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Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor

Abstract : In this paper, we present an improved methodology to extract the small-signal electrical equivalent circuit of the parasitic elements using RF test structures for a 3D vertical nanowire transistor technology. The methodology is based on the extraction of the distributed parasitic elements from an open structure for which on-wafer S-parameter measurements were carried out up to 40 GHz. The electrical equivalent circuit of the passive device was then used for de-embedding of the transistor S-parameters for extraction of intrinsic smallsignal parameters such as the gate capacitances.
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https://hal.archives-ouvertes.fr/hal-03657781
Contributor : Chhandak Mukherjee Connect in order to contact the contributor
Submitted on : Tuesday, May 3, 2022 - 12:18:25 PM
Last modification on : Monday, July 4, 2022 - 10:19:30 AM
Long-term archiving on: : Thursday, August 4, 2022 - 6:27:26 PM

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Bruno Neckel Wisling, Marina Deng, Chhandak Mukherjee, Magali de Matos, Abhishek Kumar, et al.. Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor. Solid-State Electronics, Elsevier, 2022, 194, pp.108359. ⟨10.1016/j.sse.2022.108359⟩. ⟨hal-03657781⟩

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