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Contribution to the development of massively parallel radio frequency SoC architectures in advanced CMOS technologies

Reda Kasri 1
1 LAAS-MOST - Équipe Microondes et Opto-microondes pour Systèmes de Télécommunications
LAAS - Laboratoire d'analyse et d'architecture des systèmes
Abstract : During the last decade, a trend in receiver design has been to integrate more and more tuners on the same chip. When implemented using analog tuners, each tuner requires its own PLL and inductor VCO, increasing chip area and power, while introducing interference issues between uncorrelated frequencies. Digitizing the whole spectrum, also known as Full Spectrum Capture (FSC), moves the channel selection and processing to digital. It allows a high number of received channels on the same chip, while only one clock is required. However, FSC puts a heavy burden on the ADC and digital processing, leading to a high and fixed power consumption as the FSC system samples the entire band, even when only a few channels are needed. To reduce the FSC-power burden, this thesis proposes a power efficient and power scalable architecture. It exploits a mixer-DAC driven by Direct Digital Frequency Synthesis (DDFS) for each channel, using all a single clock. We target 40dB dynamic range (8-bit DDFS-mixer-DAC), which is sufficient for many upcoming applications. We exploit 28nm UTBB FD-SOI CMOS technology, as it has low power digital signal processing capabilities and good MOSFET characteristics even at short channel lengths. Our circuit is based on a mixer-DAC that exploits 8 binary scaled transconductances driven by the same RF-voltage, while summing their currents at the output. The output current is thus the product of the analog input voltage and the digital code (DDFS output) that varies over time as a sampled walking sinewave. This realizes a multiplying-DAC or mixer-DAC. Using a sinewave-like mixing signal enhances conversion gain by π/2, and improves NF. The binary weighting is implemented putting identical switched-Gm mixer slices in parallel. If enabled, it operates as a linear and low noise CMOS inverter, which has favorable properties like high linearity, class-AB behavior and current re-use. A differential load made of two capacitors is implemented. The two switched capacitors act like an N-path band pass filter and improve the robustness of the receiver for interfering channels non-linearities. A demonstrator with two parallel tuners receiving two uncorrelated frequencies were implemented. Each tuner consumes 9.5mW with a gain of 20 to 30dB, an NF from 7 to 13dB, an image rejection of 42 dB and more than 43 dB of harmonic rejection. Finally, cross-talk rejection between the two tuners'clocks was measured and is superior to 75 dB, which is a high enough value to confirm the adequacy of our architecture for a future development with a lot of tuners in parallel.
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Submitted on : Monday, January 21, 2019 - 2:10:17 PM
Last modification on : Thursday, June 10, 2021 - 3:02:24 AM


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  • HAL Id : tel-01987950, version 1


Reda Kasri. Contribution to the development of massively parallel radio frequency SoC architectures in advanced CMOS technologies. Micro and nanotechnologies/Microelectronics. Université Toulouse 3 Paul Sabatier (UT3 Paul Sabatier), 2017. English. ⟨tel-01987950⟩



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