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Transistor de puissance à structure verticale et à cathode en tranchée

Moustafa Zerarka 1 Patrick Austin 1 Marise Bafleur 2
1 LAAS-ISGE - Équipe Intégration de Systèmes de Gestion de l'Énergie
LAAS - Laboratoire d'analyse et d'architecture des systèmes
2 LAAS-ESE - Équipe Énergie et Systèmes Embarqués
LAAS - Laboratoire d'analyse et d'architecture des systèmes
Abstract : The invention relates to a vertically structured power transistor, such as a VD-MOS or an IGBT, having a cell comprising: two symmetrical source layers (308), preferably N+ doped, which extend from a front surface (312) of the semiconductor substrate; a well layer (307), preferably P doped, comprising an area having a higher doping concentration (307b) that extends from one source layer to the other; a source/well NP junction (J3) between the source layer and the well layer. According to the invention, a cathode formed on the front surface (312) of the semiconductor substrate has a trench portion (309) with a bottom (313) that extends into the area having a higher doping concentration (307b) of the well layer (307) to a certain depth away from the source/well NP junction (J3)
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https://hal.laas.fr/hal-01844068
Contributor : Marise Bafleur <>
Submitted on : Thursday, July 19, 2018 - 10:18:25 AM
Last modification on : Thursday, June 10, 2021 - 3:02:48 AM

Identifiers

  • HAL Id : hal-01844068, version 1

Citation

Moustafa Zerarka, Patrick Austin, Marise Bafleur. Transistor de puissance à structure verticale et à cathode en tranchée. France, Patent n° : FR3029014-A1. Rapport LAAS n° 16668. 2016, 26p. ⟨hal-01844068⟩

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